Altera Integer Arithmetic IP - Manual (Page 44)

The following Verilog HDL prototype is located in the Verilog Design File (.v) lpm.v in the <Quartus II
installation directory>\eda\synthesis directory.
module altecc_decoder
#( parameter intended_device_family = "unused",
parameter lpm_pipeline = 0,
parameter width_codeword = 8,
parameter width_dataword = 8,
parameter lpm_type = "altecc_decoder",
parameter lpm_hint = "unused")
( input wire aclr,
input wire clock,
input wire clocken,
input wire [width_codeword-1:0] data,
output wire err_corrected,
output wire err_detected,
outut wire err_fatal,
output wire [width_dataword-1:0] q);
endmodule
VHDL Component Declaration (ALTECC_ENCODER)
The VHDL component declaration is located in the VHDL Design File (.vhd)
altera_mf_components.vhd in the <Quartus II installation directory>
\libraries\vhdl\altera_mf directory.
component altecc_encoder
generic (
intended_device_family:string := "unused";
lpm_pipeline:natural := 0;
width_codeword:natural := 8;
width_dataword:natural := 8;
lpm_hint:string := "UNUSED";
lpm_type:string := "altecc_encoder");
port(
aclr:in std_logic := '0';
clock:in std_logic := '0';
clocken:in std_logic := '1';
data:in std_logic_vector(width_dataword-1 downto 0);
q:out std_logic_vector(width_codeword-1 downto 0));
end component;
VHDL Component Declaration (ALTECC_DECODER)
The VHDL component declaration is located in the VHDL Design File (.vhd)
altera_mf_components.vhd in the <Quartus II installation directory>
\libraries\vhdl\altera_mf directory.
component altecc_decoder
generic (
intended_device_family:string := "unused";
lpm_pipeline:natural := 0;
width_codeword:natural := 8;
width_dataword:natural := 8;
lpm_hint:string := "UNUSED";
lpm_type:string := "altecc_decoder");
port(
aclr:in std_logic := '0';
clock:in std_logic := '0';
clocken:in std_logic := '1';
5-6 VHDL Component Declaration (ALTECC_ENCODER)
UG-01063
2014.12.19
Altera Corporation ALTECC (Error Correction Code: Encoder/Decoder)
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