Altera Integer Arithmetic IP - Manual (Page 55)

For Stratix V devices, the multiplier blocks and adder/accumulator block is combined in a single MAC
block.
The multipliers and adders of the ALTERA_MULT_ADD megafunction are placed in the dedicated DSP
block circuitry of the Stratix devices. If all of the input data widths are 9-bits wide or smaller, the function
uses the 9 × 9-bit input multiplier configuration in the DSP block. If not, the DSP block uses 18 × 18-bit
input multipliers to process data with widths between 10 bits and 18 bits. If multiple
ALTERA_MULT_ADD megafunctions occur in a design, the functions are distributed to as many
different DSP blocks as possible so that routing to these blocks is more flexible. Fewer multipliers per DSP
block allow more routing choices into the block by minimizing paths to the rest of the device.
The registers and extra pipeline registers for the following signals are also placed inside the DSP block:
• Data input
• Signed or unsigned select
• Add or subtract select
• Products of multipliers
In the case of the output result, the first register is placed in the DSP block. However the extra latency
registers are placed in logic elements outside the block. Peripheral to the DSP block, including data inputs
to the multiplier, control signal inputs, and outputs of the adder, use regular routing to communicate with
the rest of the device. All connections in the function use dedicated routing inside the DSP block. This
dedicated routing includes the shift register chains when you select the option to shift a multiplier's
registered input data from one multiplier to an adjacent multiplier.
For more information about DSP blocks in any of the Stratix, Stratix GX, and Arria GX device series, refer
to the DSP Blocks chapter of the respective handbooks on the Literature and Technical Documentation
page.
For more information about the embedded memory blocks in any of the Stratix, Stratix GX, and Arria GX
device series, refer to the TriMatrix Embedded Memory Blocks chapter of the respective handbooks on the
Literature and Technical Documentation page.
For more information on embedded multiplier blocks in the Cyclone II and Cyclone III devices, refer to
the DSP Blocks chapter of the respective handbooks on the Literature and Technical Documentation
page.
For more information about implementing multipliers using DSP and memory blocks in Altera FPGAs,
refer to AN 306: Implementing Multipliers in FPGA Devices .
Features
The ALTERA_MULT_ADD megafunction offers the following features:
• Generates a multiplier to perform multiplication operations of two complex numbers
Note: When building multipliers larger than the natively supported size there may/will be a perform‐
ance impact resulting from the cascading of the DSP blocks.
• Supports data widths of 1– 256 bits
• Supports signed and unsigned data representation format
• Supports pipelining with configurable output latency
• Provides an option to dynamically switch between signed and unsigned data support
6-2 Features
UG-01063
2014.12.19
Altera Corporation ALTERA_MULT_ADD (Multiply-Adder)
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