Altera Arria 10 Avalon-MM DMA User Manual
User guide
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Table of contents
Document Outline
- Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
- Contents
- 1. Datasheet
- 2. Getting Started with the Avalon-MM DMA
- Generating the Testbench
- Simulating the Example Design in ModelSim
- Running a Gate-Level Simulation
- Generating Quartus II Synthesis Files
- Creating a Quartus II Project
- Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)
- Compiling the Design
- Descriptor Controller Connectivity when Instantiated Separately
- 3. Parameter Settings
- 4. Physical Layout of Hard IP In Arria 10 Devices
- 5. IP Core Interfaces
- Arria 10 DMA Avalon-MM DMA Interface to the Application Layer
- Clock Signals
- Reset, Status, and Link Training Signals
- MSI Interrupts for Endpoints
- Hard IP Reconfiguration Interface
- Physical Layer Interface Signals
- 6. Registers
- Correspondence between Configuration Space Registers and the PCIe Specification
- Type 0 Configuration Space Registers
- PCI Express Capability Structures
- Altera-Defined VSEC Registers
- CvP Registers
- Uncorrectable Internal Error Mask Register
- Uncorrectable Internal Error Status Register
- Correctable Internal Error Mask Register
- Correctable Internal Error Status Register
- DMA Descriptor Controller Registers
- Control Register Access (CRA) Avalon-MM Slave Port
- 7. Arria 10 Reset and Clocks
- 8. Error Handling
- 9. IP Core Architecture
- 10. Design Implementation
- A. Frequently Asked Questions
- B. Additional Information