Altera POS-PHY Level 4 IP Core - Manual (Page 111)

Appendix A: Start-Up Sequence A–5
Troubleshooting
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
data output, and the phase relation can be selected. There are notes on how to
do this in the top-level file. In either case the functional simulation models
need to be refreshed using the tool command language (Tcl) script provided.
Refer to the
SERDES Transmitter/Receiver (ALTLVDS) IP Core User Guide for
details.
■ This issue could be jitter related. Try adjusting the bandwidth of the PLLs. In
the fast PLLs, embedded in the ALTLVDS IP core, this is done by adding a
pll_bandwidth_type
parameter to the ALTLVDS instance. This parameter can
be low, medium, high, and defaults to auto, which should be high. The following
code is a Verilog HDL code example:
altlvds_rx_component.pll_bandwidth_type = "low"
■ Ensure the LVDS input pins have differential termination resistors. Some
devices do not contain internal termination resistors (check the device
datasheet), so you must place the 100 ohm resistors externally. For Altera
development kits, ensure you mount the termination resistors on the board.
6. Receiver (particularly third-party receivers) detects protocol errors related to burst
length. The following tips may prove useful:
■ If the transmitter is an embedded address variation, ensure that bursts are
written into the FIFO buffer in multiples of ctl_td_burstlen, or eop
terminated.
■ Ensure that ctl_td_burstlen is less than the buffer size.
7. Throughput is lower than expected. The following tips may prove useful:
■ Understand quantization effects and choose transmitter mode (lite or non-lite),
data path width, and clock frequencies appropriate for your packet size and
throughput needs.
■ Ensure all clocks are operating at their specified frequencies.
■ Ensure transmitter queue(s) always has data, otherwise factor into expectation.
■ Ensure receiver queue(s) always has space, otherwise factor into expectation.
■ Ensure status is sent or received as expected, which includes checking
stat_ts_sync
, stat_td_holb, ctl_ts_status_mode, ctl_ry_fifostatoverride,
ctl_ry_ae and ctl_ty_af.
■ Ensure credits (ctl_td_mb1 and ctl_td_mb2) are large enough that they do not
run out between status updates.
Issues and Tips—Miscellaneous
Miscellaneous unexpected behavior:
■ Ensure all clocks are up and operating at their specified frequencies.
■ Ensure all resets have been asserted, and released only after clock stabilization.
■ Ensure all signals connected to the IP core are driven or sampled with the
appropriate clock.
■ Ensure all parameters are set as specified.