Altera POS-PHY Level 4 IP Core - Manual (Page 79)

Chapter 5: Functional Description—Transmitter 5–9
Clock Structure
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
Multiple Clock Domain
In multiple clock domain mode, the tdint_clk clocks the protocol logic of the IP core,
and the read side of the Atlantic FIFO buffers.
In multiple clock mode, an extra input clock is instantiated for each Atlantic FIFO
buffer in the IP core, which is used for the write side of the buffers. The naming
convention for these input clocks is aN_atxclk. These clocks are inputs to the IP core
and can either be tied together or controlled individually.
Table 5–1 shows the clock frequency values for a data rate of 800 Mbps on the SPI-4.2
bus.
Table 5–1. Clock Domains
Clock Domain Description
Transmit IP core clock
(trefclk/tdint_clk)
The trefclk clock is the input to the IP core. The tdint_clk clock is an output wire, and is
the output of a fast PLL. The trefclk can be generated from multiple possible sources, for
various frequencies. For example, a SPI-4.2 bus rate of 800 Mbps requires a 100 MHz clock
for a data path width of 128 bits, a 400 MHz clock for a data path width of 32 bits, and a 200
MHz clock for a data path width of 64 bits.
Transmit status channel
clock (tsclk)
The SPI-4.2 specification specifies a maximum status clock of ¼ of the tdclk frequency.
This clock may be independent of tdclk. For example, it is possible to have a frequency of
100 MHz or less for a data path width of 128 or 64 bits, and of 25 MHz or less for a data path
width of 32 bits.
System clock (txsys_clk)
The txsys_clk frequency must be faster than, or equal to, the tsclk frequency. This clock
transfers status to the external status interface.
Transmit Atlantic clock
(aN_atxclk)
This clock is typically asynchronous to trefclk, but this is not a restriction. In the
individual buffers mode, there may be as many clock domains as there are ports, and they
are all allowed to be of different phase and frequency.