Altera POS-PHY Level 4 IP Core - Manual (Page 27)

Chapter 3: Parameter Settings 3–7
Optional Features
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
The missing SOP and missing EOP error indicators are always zero if you turn off
Atlantic error checking
.
Turn on Parity protected memory to protect all Atlantic FIFO buffers in the IP core by
byte-lane parity. The parity is calculated across every byte of data that is written to
memory in the buffers, and is checked for correctness when it is read. If a parity error
is detected, an error signal is raised. Turn off Parity protected memory, to deactivate
the parity protection.
1 In the receive direction, the parity error signal is 2 clock cycles delayed (compared to
Atlantic FIFO read data). In the transmit direction, the parity error signal is 1 or 2
clock cycles delayed (compared to Atlantic FIFO read data) depending on the
parameters selected.
Transmitter Options
When you turn on Lite transmitter, the transmitter pads packets with IDLE characters
to a multiple of 16 bytes for 128-bit variations, or 8 bytes for 64-bit variations.
Although using the lite transmitter feature lowers the effective bandwidth rate on the
SPI-4.2 data bus, it greatly reduces the logic consumption.
When you turn off Lite transmitter, the transmitter packs the packets more tightly
together and pads them with IDLE characters to a multiple of 4 bytes. SOP,
continuation of packet (COP) and EOP may be combined into a single control word,
or may be in adjacent control words. Turning off the lite transmitter feature increases
the effective bandwidth rate on the SPI-4.2 data bus, but increases the logic
consumption.
1 COP means no SOP. COP can be pure continuation (control word bits [15:12] =
4'b1000
, so no SOP and no EOP, but payload follows) or EOP + continuation (control
word bits [15:12] = 4'b1xx0, so end current packet, but continue other packets).
For the transmitter IP core you can select Pessimistic or Optimistic for the Status
interpretation mode
.
In the Pessimistic mode, the latest status information is captured and is stored inside
the status processor block until a DIP-2 status is received. If the DIP-2 is valid, the
buffered status is passed on to the scheduler or user logic. If the DIP-2 is invalid, the
scheduler and user logic do not receive an update, and the next incoming status
overwrites the errored buffered status.
In the Optimistic mode, the status information is provided to the user logic and
scheduler through a clock-crossing buffer as it arrives on the status channel. DIP-2
errors cause the err_ts_dip2 flag to be asserted, but do not affect the status reception.
1
The Pessimistic mode causes the latency in receiving a valid status message to be
calendar multiplier × calendar length tsclk cycles longer than the optimistic mode. This
length is significant for systems with large calendar length or large calendar
multiplier values.