Altera POS-PHY Level 4 IP Core - Manual (Page 60)

4–22 Chapter 4: Functional Description—Receiver
Error Flagging and Handling
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
Missing EOP
Figure 4–11 and 4–22 show that if a SOP is detected during an open packet, the
err_ry_meop signal is asserted, an EOP is forced, the err signal is asserted, and data is
ignored for that port until an EOP is received.
Figure 4–11. Missing EOP Input Timing Diagram
Figure 4–12. Missing EOP Output Timing Diagram
Packet A Packet B
aN_atxeop
aN_atxerr
aN_atxtclk
aN_atxena
aN_atxsop
err_ry_meop
aN_arxeop
aN_arxerr
aN_arxtclk
aN_arxena
aN_arxsop
Figure 4–13. Overflow
SS
SS
SS
SS
SS
aN_rxclk
aN_arxena
aN_arxsop
aN_arxeop
err_ry_fifo_oflwN
aN_arxdav
Good Packet Interrupted Packet(s) Good Packet