Altera POS-PHY Level 4 IP Core - Manual (Page 42)

4–4 Chapter 4: Functional Description—Receiver
Block Description
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
To compensate for large amounts of static channel-to-channel skew, the POS-PHY
Level 4 IP core channel aligner state machine uses the bit slip feature (the channel
align or data realignment) of the ALTLVDS_RX IP core.
The POS-PHY Level 4 IP core automatically configures and includes the
ALTLVDS_RX IP core.
Channel Aligner
The DPA feature of the ALTLVDS_RX IP core provides parallel data sampled correctly
and aligned to a single clock. As it does not use a data pattern, it cannot compensate
for more than one bit time of channel-to-channel skew which may exist due to trace
length mismatches.
The channel aligner sub-block uses the SPI-4.2 training pattern to align the parallel
data. Alignment is done once at start-up, and then only when requested by asserting
the ctl_rd_dpa_force_unlock signal. The channel aligner state machine begins the
alignment process once the ctl_rd_dpa_force_unlock signal is deasserted and the
altlvds_rx IP core asserts the stat_rd_dpa_lvds_locked signal (high). It then pulses
the bits of the align[16:0] signal channel by channel until all channels are aligned,
which can be detected by looking for the repeating training pattern. For every align
pulse, the ALTLVDS_RX IP core sub-block shifts the data on the corresponding
channel by one bit, effectively in the serial domain. The actual shift occurs in the serial
domain for Stratix III and Stratix II devices, and in the parallel domain for Stratix GX
devices.
In Stratix III and Stratix II devices, the IP core requires less than 220 training patterns
(lock time) before it asserts the stat_rd_dpa_lvds_locked signal. The err_rd_dpa
signal is tied low.
In Stratix GX devices, the IP core requires less than 700 training patterns (lock time)
before it asserts the stat_rd_dpa_locked signal. If alignment cannot be achieved
because of a large skew between data channels, or because the
stat_rd_dpa_lvds_locked
signal becomes deasserted during training, the channel
aligner asserts the err_rd_dpa signal.
8:4 Serializer
The 8:4 serializer block supports an overall deserialization factor of 4 for 64-bit
Stratix GX variations only. It consists of a PLL and a 2:1 multiplexer for each channel.
f
For more information on using dynamic phase alignment, refer to Appendix F, Static
and Dynamic Phase Alignment .
Data Processor (rx_data_proc)
The data processor consists of three sub-blocks.
Control Word Processing & DIP-4
The control word processing and DIP-4 block analyses the control words from the
data stream, and calculates the running DIP-4 value. It detects the following errors: