Altera POS-PHY Level 4 IP Core - Manual (Page 117)

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
D. Board Design
Pin Constraints
The pinouts for the Stratix ® GX, and Stratix device families include dedicated LVDS
clock input pins located on either the RXCLK_IN1n/p bank, or the RXCLK_IN2n/p bank.
For the Stratix IV, Stratix III and Stratix II device families, the dedicated LVDS clock
input pins are located on a minimum of two banks. You should try to keep all pins for
the receiver on the same bank. However, for Stratix III devices, if you cannot keep all
receiver pins in one I/O bank, use two adjacent banks. These LVDS banks require a
clean, filtered, power supply.
Board Design Configuration
f For detailed board layout guidelines, refer to AN 224: High-Speed Board Layout
Guidelines .
f For detailed board layout guidelines in Stratix III and Stratix II devices, refer to the
High-Speed Board Layout Guidelines and High-Speed Differential I/O Interfaces with DPA in
Stratix II Devices chapters of the Stratix II Device Handbook.
f For detailed board layout guidelines in Stratix devices, refer to the High-Speed
Differential I/O Interfaces in Stratix Devices chapter of the Stratix Device Handbook.
You should use a parallel combination of 0.1, 0.01, and 0.001 F capacitors to decouple
the high-speed phase-locked loop (PLL) power and ground planes.
If the status lines are not shifted by 180 degrees as per the SPI-4 Phase 2 specification,
the sampling window can be shifted internally. For tstat lines, this shift is
accomplished by sampling on the negative edge of tsclk instead of the positive edge.
The rstat lines can also be flopped out on the negative edge to phase shift the data for
the adjacent device.
For the output clock (tdclk), you should not use the LVDS output clock pins, but
should use an appropriate LVDS data pair instead. Clock pins can be treated as data
pins, because the serializer/deserializer (SERDES) is preloaded with a binary 1010
pattern that guarantees an appropriate skew between the clock and data.
As for LVDS traces running at 500 Mbps or higher, the standard board layout
guidelines for laying out high-speed LVDS traces should apply.
1
Give special attention to status channel lines, to ensure setup and hold time
requirements are met. Trace lengths should match.
Design for Testability
High speed designs involving SPI-4.2 interfaces can be very complex. Altera
recommends that you design the circuit board with debug testability in mind. This
section describes recommended practices to follow while designing the board.