Altera POS-PHY Level 4 IP Core - Manual (Page 44)

4–6 Chapter 4: Functional Description—Receiver
Block Description
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
■ Buffer status interface
■ Overflow error indication
■ Underflow warning indication
■ Configurable FIFO buffer threshold low (FTL)
■ Optional end-of-packet-based data available (aN_arxdav) signal assertion
■ Atlantic interface error checking
■ Missing or spurious SOP/EOP detection and correction
■ Optional overflow handling
Shared Buffer with Embedded Addressing
When the shared buffer with embedded addressing mode is selected, the POS-PHY
Level 4 IP core consists of the receiver processor logic and a shared FIFO buffer with
embedded addressing.
The shared buffer is a single Atlantic FIFO buffer, where for each data word a tag is
carried containing the port number. This means that the Atlantic-side logic cannot
selectively pick a port to access. Instead, data bursts from all ports are stored
collectively into this one shared physical buffer, and the ordering of the data bursts is
maintained in the order in which they were received on the SPI-4.2 bus.
The shared buffer and the logic support up to 256 ports. If Atlantic error checking is
enabled, 256 ports are still supported by the IP core, but the logic for error checking
uses only the minimum amount of logic required to support the number of ports
chosen as a parameter. The port width field remains fixed for 256 ports and unused
address bits are passed through unaffected. For example, if a variation has 4 ports,
only the lower 2 address bits are used for error checking—data received for port 6 is
checked as though it is for port 2. This allows unused upper address bits to be used
for packet classification.
The single FIFO buffer with embedded addressing supports interleaved packets. An
interleaved packet occurs when, for example, a packet from port 2 is sent, and then a
packet from port 3 is sent before port 2 has received the EOP indication. This
interleaving is achieved by changing the aN_arxadr in the middle of the packet.
The shared buffer with embedded addressing mode is useful if you intend to handle
buffering outside of the IP core. To support user-defined external buffering, a fully
exposed status interface is provided, but requires that the status channel override
(status source parameter) be enabled. Normally, the shared buffer with embedded
addressing fill level is compared against the global almost empty (AE) and almost full
(AF) values to produce the status information for all ports on the status channel. With
the override feature, you can set the FIFO buffer status information values on a per-
port basis.
Individual Buffers
When the individual buffers mode is selected, the POS-PHY Level 4 IP core consists of
the receiver processor logic, and a separate Atlantic FIFO buffer for each port.