Altera POS-PHY Level 4 IP Core - Manual (Page 77)

Chapter 5: Functional Description—Transmitter 5–7
Block Description
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
When the ignore backpressure feature is turned off (always off for the individual
buffers mode), and the status channel informs the Atlantic converter that one port is
satisfied, all ports stop sending.
Status Channel Interpretation Modes
The status FIFO buffers of the transmitter IP core support two status channel
interpretation modes: pessimistic and optimistic. The mode is applied to the status
sent to the scheduler (individual buffers mode) and to the user logic.
Pessimistic Mode
The last calendar length of the incoming status frame is stored in a FIFO buffer until a
DIP-2 is received. If a DIP-2 containing errors is received, the status from that frame is
dropped, and the transmit scheduler does not get any new credits. If the DIP-2 is
errorless, the status is sent to the user logic and scheduler.
1
The pessimistic mode causes the latency in receiving a valid status message to be
calendar multiplier × calendar length tsclk cycles longer than the optimistic mode. This
is significant for systems with large calendar length or large calendar multiplier
values.
Optimistic Mode
The status information is provided to the user and transmit scheduler as soon as it can
pass through the clock-crossing FIFO buffers, before the DIP-2 cycle is even received.
DIP-2 errors are flagged, but have no effect on the status provided to the user, or to the
scheduler.
1 In either mode, the stat_ts_dip2state signal indicates when a DIP-2 has been
received at the finite state machine.
Status Bypass Port
The status bypass port copies the values of the status signals going to the IP core. DIP-
2 errors are not calculated on this port. The port is output only and can therefore be
left unconnected or undeclared. This interface provides the following signals on the
tsclk
:
■ stat_ts_sync
■ stat_ts_disabled
■ stat_ts_dip2state
■ stat_ts_frmstate
■ stat_ts_extstat_adr
■ stat_ts_extstat
f
For more information on the signals, refer to Table 5–7 on page 5–19 .