Status processor – Altera POS-PHY Level 4 IP Core User Manual
Page 45
Chapter 4: Functional Description—Receiver
4–7
Block Description
December 2014
Altera Corporation
POS-PHY Level 4 IP Core User Guide
The advantage of the individual buffers mode is that each Atlantic interface can be
accessed in parallel and independently, and the IP core handles the status generation
automatically. The disadvantage is that because the number of ports directly increases
the logic utilization, the individual buffers mode is not well suited for applications
with a large number of ports.
Status Processor
A major component of a SPI-4.2 system is flow control. Flow control is achieved by
periodically sending near-end FIFO buffer status to the far-end device’s scheduler
over the status channel.
Collectively, the status processor blocks calculate, format, and transmit the status
channel.
Starting at the physical interface and working back to the FIFO buffers, the flow
control has the following operation.
The status PHY block (rx_stat_phy) generates rsclk given some reference clock:
■
In 128-bit variations, the rsclk runs at the rdint_clk rate.
■
In 64-bit variations, the rsclk runs at 1/2 the rdint_clk rate.
■
In 32-bit variations, the rsclk runs at 1/4 of the rdint_clk rate.
The status PHY block aligns rstat to either the positive or negative edge of rsclk
depending on the input value of the ctl_rs_statedge signal. This block also
implements a clock-crossing FIFO buffer between the rsclk and rxsys_clk domains.
The status FSM block (rx_stat_proc_fsm) is enabled when the clock-crossing FIFO
buffer of the status PHY block has available space. When enabled, this block generates
the next words in the status frame.
If the clock-crossing FIFO buffer underflows or overflows because of an incorrect
configuration, if the ctl_ry_rsfrm signal is set, or if the rsfrm bit in the Avalon
®
Memory-Mapped (Avalon-MM) interface is set, the finite state machine outputs ‘11’
continuously and the stat_ry_disabled signal is asserted.
Framing, calendar select word, and DIP are generated locally, but the actual status for
each calendar slot is provided on request by the status register (rx_stat_proc_reg)
block, and either the status calculator (rx_stat_calc) or status hold (rx_stat_hold)
blocks.
Given a calendar slot number, the status register block determines which port's status
belongs in the slot according to the calendar that it stores. When the asymmetric port
support parameter is turned off, the port number corresponds with the slot number,
(that is, slot one is port one, and so on). When the asymmetric port support parameter
is turned on, a programmable calendar is stored in memory, and the port
corresponding to the slot is looked up.
1
If the asymmetric port support parameter is turned on, the Avalon-MM registers must
be programmed prior to releasing the rsfrm bit (refer to
and the