Altera POS-PHY Level 4 IP Core - Manual (Page 23)

Chapter 3: Parameter Settings 3–3
Basic Parameters
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
IP Toolbench uses the LVDS data rate to instantiate and parameterize the ALTLVDS
IP core that includes the fast PLL. For example, for a receiver with a data rate of
700 Mbps on each rdat line, enter 700 in LVDS data rate. This value corresponds to a
350 MHz double-data rate (DDR) clock on rdclk.
PLL Input Frequency
For a transmitter only, you can enter the PLL input frequency. To enter the PLL
frequency, you must click Import PLL Frequency, to open the ALTLVDS wizard and
view the available input PLL frequencies.
1
When you change the data path width, the PLL input frequency changes.
1 Do not type the PLL frequency into the box.
Data Path Width
The Data path width affects two important aspects of the IP core: size and
performance. The IP core offers the following options:
■ 128 bits running at a frequency of 1/8 the LVDS data rate
■ 64 bits running at 1/4 the LVDS data rate
■ 32 bits (quarter rate) running at 1/2 the LVDS data rate (for non-standard
applications at a maximum of 250 Mbps)
f For approximate resource usage and performance of example POS-PHY Level 4
variations, refer to
“Performance and Resource Utilization” on page 1–5 .
Buffer Mode
The POS-PHY Level 4 IP core supports the following two buffer modes:
■ Shared buffer with embedded addressing
■ Individual buffers
With Shared buffer with embedded addressing, all ports share a single Atlantic
buffer with an 8-bit address field that supports up to 256 ports. The data is read from
the Atlantic buffer in the same order as it is received. The shared buffer with
embedded addressing mode is smaller than the individual buffers mode, and allows
you to develop your own buffering and status generation implementation.
With Individual buffers, the POS-PHY Level 4 IP core provides an Atlantic first-in
first-out (FIFO) buffer for each port. Therefore, there are as many Atlantic FIFO
buffers of the same depth and width—each with a unique Atlantic interface on the
user end—as the number of ports that you select. The individual buffers supports up
to 16 ports.
1 Timing and routing difficulties may occur when using 16 ports for 128 bit variations;
thus a maximum of 10 ports is recommended for 128-bit variations.