Rockwell Automation 1756-DHRIO_DHRIOXT ControlLogix Data Highway Plus-Remote I/O Communication Interface Module - Manual (Page 165)

Rockwell Automation Publication 1756-UM514C-EN-P - June 2014 165
Application Guidelines and Tips Appendix B
• We recommend that the number of uncached messages enabled in your
application be no more than 50% of your UCB limit. For example, if you
are using the 40 UCB limit, we recommend that no more than 20
uncached messages are enabled at once.
If your application requires that more uncached messages are enabled than
50% of your UCB, manage the messages to make sure that only a total of
50% are enabled at any single time. For example, if your application uses
the 10 UCB limit but requires 7 uncached messages, make sure only a total
of 5 uncached messages are active at any time.
• If the message is giving error #301 that means the UCB is full
Message Manager Even though the unconnected message buffer can be increased to 40, the best
throughput performance is attained when only 5 messages are enabled in a
ControlLogix controller at one time. One simple method of managing your
messages is to enable five messages, wait for all five to complete and than enable
another set of five messages. Repeat the process as needed until all required
message completed.
Messages Between a
ControlLogix Controller and
PLC Devices For more information on the 1756-DHRIO or 1756-DHRIOXT module’s
performance when messages are sent between a ControlLogix controller and
PLC devices, see the Rockwell Automation Knowledge Base. The database can
be accessed from the following location:
https://rockwellautomation.custhelp.com/
RPI Configuration Settings • Requested Packet Interrupt (RPI) setting on the 1756-DHRIO and
1756-DHRIOXT modules is the time where the DHRIO module sends
status information to the controller. It is not the time where data is
transferred from the DHRIO to the controller.
• RPI setting for adapter modules are used to send discrete data from the
adapter racks to the controller
• All adapter racks underneath the same channel of a DHRIO module are
set to the same RPI time
• Block Transfer data is updated during the time slice period as specified in
the ControlLogix controller