Altera CPRI IP Core - Manual (Page 168)

C–6 Appendix C: CPRI Autorate Negotiation Testbench
Running the Autorate Negotiation Testbench
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
3. If you are running the testbench for a Stratix IV GX or Cyclone IV GX variation,
you must generate the appropriate Memory Initialization Files (.mif) to configure
the altgx_reconfig block. If you are running the testbench for a Cyclone IV GX
variation, the following steps also generate the appropriate .mif files to configure
the altpll_reconfig block. To generate the files, perform the following steps:
a. On the Assignments menu, click Settings.
b. In the Settings dialog box, under Category, click Fitter Settings.
c. Click More Settings.
d. Turn on Generate GXB Reconfig MIF by clicking in the Setting column and
selecting On.
e. Click OK.
f. Click Apply.
g. Click OK.
h. On the Processing menu, click Start Compilation.
After compilation completes, the following newly generated .mif files are
available, depending on your target device:
reconfig_mif/stratix4gx_
<rate>_m.mif, cyclone4gx_<rate>_m_rx_pll1.mif,
cyclone4gx_ <rate>_m_tx_pll0.mif, reconfig_mif/cyclone4gx_<rate>_m.mif.
i. In the MegaWizard Plug-In Manager, edit the existing CPRI IP core variation,
change its data rate to 0.6144 Gbps, and regenerate to create the DUT. When
you are prompted to generate an example design, turn on Generate Example
Design
and click Generate. You run the testbench with this variation.
j. Repeat step h . A new set of .mif files is generated for the new data rate.
k. Move all of the .mif files from the working directory (the .mif files to configure
the altpll_reconfig block are the only .mif files in this directory) to the
reconfig_mif
subdirectory, <working dir>/reconfig_mif.
4. If you are running the default autorate negotiation testbench for 28-nm device
variations, full compilation automatically generates the appropriate Memory
Initialization Files (.mif) to configure the Altera Transceiver Reconfiguration
Controller. However, you must perform the full compilation at the 0.6144 Gbps
CPRI line rate, to generate the .mif for the lower line rate, before you run the
testbench at the 1.2288 Gbps line rate.
Altera recommends that you compile Arria V, Cyclone V, and Stratix V designs
with the 64-bit Quartus II software.
To generate the .mif and prepare for simulation, perform the following steps:
a. On the Processing menu, click Start Compilation.
After compilation completes, the newly generated .mif files
inst_xcvr_channel.mif
and inst_xcvr_txpll0.mif are available in the
reconfig_mif subdirectory of the project.