Altera CPRI IP Core - Manual (Page 55)

Chapter 4: Functional Description 4–23
MAP Interface
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
1 In advanced mapping modes, the K counter is reset to zero at the same time, so that it
advances from zero with the transfer of the data to the MAP Rx buffer, tracking the
packing of the CPRI data contents into the AxC container block.
Because the mapN Rx buffer should not be read before it is written, the offset
specified in the
CPRI_MAP_OFFSET_RX register must precede the offset specified in the
CPRI_START_OFFSET_RX register. The CPRI IP core informs you of buffer overflow and
underflow (in the CPRI_IQ_RX_BUF_STATUS register described in Table 7–48 on
page 7–22 , as reported in the mapN_rx_status_data output signals described in
Table 6–1 on page 6–1 ), but it does not prevent them from occurring. Altera
recommends that you implement a separate tracking protocol to ensure you do not
overflow or underflow the mapN Rx buffer.
You set the values in the CPRI_START_OFFSET_RX and CPRI_MAP_OFFSET_RX registers to
specify the timeslot in the 10 ms radio frame in which your application expects to
sample the data on the antenna-carrier interface.
In synchronous buffer mode, because programmed offsets control the mapN Rx
buffer pointers, the delay through each mapN Rx buffer can be quantified.
1 In synchronous buffer mode, Altera recommends that you use sample rates that are
integer multiples of 3.84 MHz, or for implementing the WiMAX protocol, that you use
sample rates that provide the exact frequency required.
MAP Receiver in the Internally-Clocked Mode
In the internally-clocked mode, cpri_clkout drives the antenna-carrier interfaces, in
contrast to the other two synchronization modes in which the antenna-carrier
interfaces are clocked by the input
mapN_rx_clk clocks. Each AxC interface has only a
two-stage buffer, and data passes quickly from the MAP block out to the individual
data channels. Each AxC interface has a ready output signal,
mapN_rx_start . Each
AxC interface asserts its ready signal when it first has data ready to transmit on this
data channel.
The CPRI IP core asserts the mapN_rx_start and mapN_rx_valid signals
simultaneously, synchronously with the cpri_clkout clock, when it makes data
available on the mapN_rx_data[31:0] data bus for the individual AxC interface. It
may also assert mapN_rx_valid before valid data is available. In that case, it does not
assert mapN_rx_start . In each 10 ms radio frame, for each antenna-carrier channel N ,
the application should ignore the mapN_rx_valid and mapN_rx_data signals until the
CPRI IP core asserts the mapN_rx_start signal. Refer to Figure 4–12 for an example.
For details about the behavior of the individual signals in the internally-clocked
mode, refer to
“MAP Receiver Signals” on page 6–1 .
Figure 4–12 shows an example of the behavior of the MAP Rx signals in this
synchronization mode in the basic mapping mode ( map_mode = 2’b00). The example
CPRI IP core is configured and programmed with the following features:
■ CPRI line rate is 1228.8 Mbps. Therefore the duration of a basic frame is 8
cpri_clkout cycles.
■ Three active antenna-carrier interfaces.