Altera CPRI IP Core - Manual (Page 93)

December 2013 Altera Corporation CPRI MegaCore Function
User Guide
5. Testing Features
This chapter describes the following testing features of the CPRI IP core:
■ Loopback features
■ PRBS testing features
■ RE slave link synchronization without connecting to an REC master
Loopback Modes
The CPRI IP core supports multiple loopback modes to help you test your CPRI
design.
Figure 5–1 illustrates the supported loopback paths.
The following sections describe these loopback modes.
External Loopback
The CPRI IP core supports an external loopback configuration on the CPRI link. You
can use this configuration to test the full Tx and Rx paths from an application, through
the CPRI link, and back to the application.
The CPRI testbenches provided in your CPRI IP installation configure the DUT in this
loopback mode. Refer to
Chapter 8, CPRI IP Core Demonstration Testbench .
To configure this loopback mode, you connect a CPRI REC master’s CPRI Tx interface
to its CPRI Rx interface by physically connecting the CPRI IP core’s high-speed
transceiver output pins to its high-speed transceiver input pins. As for any CPRI link,
the connection medium must support the data rate requirements of the CPRI IP core.
Altera recommends that you implement this type of loopback connection through an
SFP cable.
Figure 5–1. CPRI IP Core Supported Loopback Paths
Notes to Figure 5–1 :
(1) External loopback mode to test a single CPRI REC master.
(2) Internal reverse loopback mode configured in an RE slave’s CPRI_PHY_LOOP register.
(3) Internal reverse loopback mode configured in an RE slave’s CPRI_CONFIG register.
CPRI IP Core
CPRI Link MAP
Module
PHY
Module (1)
(2) (3)
Rx
Tx
CPRI Tx
CPRI Rx