Altera CPRI IP Core - Manual (Page 210)

F–4 Appendix F: Integrating the CPRI IP Core Timing Constraints in the Full Design
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
■ To integrate timing constraints with wild cards that identify lower level nodes in
the CPRI IP core, you must modify each lower level node designator with the
CPRI IP core instance name to ensure the new file constraints the correct design
instance of each CPRI IP core signal name.
After you perform the manual mapping and custmize the .sdc file according to this
correspondence, your file contains the correct timing constraints for the CPRI IP core
in your full design.