Altera CPRI IP Core - Manual (Page 21)

Chapter 2: Getting Started 2–5
Integrating the CPRI IP Core in a Design
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
■ Include MAC block must be turned on.
■ Number of antenna-carrier interfaces must have the value of zero.
■ Include HDLC block must be turned off.
Refer to Chapter 3, Parameter Settings for information about these parameter values.
Refer to Chapter 8, CPRI IP Core Demonstration Testbench for more information
about the non-autorate negotiation testbench and to Appendix C, CPRI Autorate
Negotiation Testbench for more information about the autorate negotiation testbench.
f For information about IP functional simulation models, refer to the Simulating Altera
Designs chapter in volume 3 of the Quartus II Handbook.
Integrating the CPRI IP Core in a Design
To compile the CPRI IP core and configure it on a device, you must integrate it in a
Quartus II project that provides additional functionality and constraints.
Supporting the Transceivers
When you integrate your CPRI IP core variation in your design, observe the following
connection requirements:
■ In Arria II, Cyclone IV GX, and Stratix IV GX designs:
■ Ensure that you connect the calibration clock ( gxb_cal_blk_clk ) to a clock
signal with the appropriate frequency range of 10–125 MHz. The cal_blk_clk
ports on other components that use transceivers must be connected to the same
clock signal.
■ Add a dynamic reconfiguration block ( altgx_reconfig ) and connect it as
specified in the Arria II Device Handbook , Cyclone IV Device Handbook , or
Stratix IV Device Handbook . This block supports offset cancellation to
compensate for analog voltages offset from required ranges due to process
variations. This block is not required for CPRI IP core autorate negotiation to
function correctly. The design compiles without the
altgx_reconfig block, but
it cannot function correctly in hardware.
■ In Arria V, Cyclone V, and Stratix V designs, add an Altera Transceiver
Reconfiguration Controller and connect it as specified in the
Altera Transceiver PHY
IP Core User Guide . This block supports offset cancellation to compensate for
analog voltages offset from required ranges due to process variations. The design
does compile without the Altera Transceiver Reconfiguration Controller, with a
critical warning, but it cannot function correctly in hardware.
Specifying Constraints
Altera provides a Synopsys Design Constraints (.sdc) file that you must apply to
ensure that the CPRI IP core meets design timing requirements. In most cases the
script requires modification for your design. For modification guidelines, refer to
Appendix F, Integrating the CPRI IP Core Timing Constraints in the Full Design .