Altera CPRI IP Core - Manual (Page 157)

December 2013 Altera Corporation CPRI MegaCore Function
User Guide
B. Implementing CPRI Link Autorate
Negotiation
The CPRI IP core supports autorate negotiation. This feature allows you to specify
that the CPRI IP core should determine the CPRI line rate at startup dynamically, by
stepping down to successively slower line rates if the low-level receiver cannot
achieve frame synchronization with the current line rate. You can provide input to the
low-level CPRI protocol interface receiver to implement this capability in your design,
with the help of logic connected outside the CPRI IP core.
If you configure your CPRI IP core for autorate negotiation, the IP core includes two
output status signals and a register to collect the status information, in addition to the
internal support to change CPRI line rate according to your design’s input to the
transceiver dynamic reconfiguration block. In Cyclone IV GX designs, the external
logic must also provide line rate information to the ALTPLL_RECONFIG
megafunction connected to the transceiver.
This appendix describes the steps you must follow and the external logic you must
include in your design to implement CPRI line rate auto-negotiation.
Design Implementation
To use the autorate negotiation feature, you must perform the following actions:
■ In the CPRI parameter editor, enable autorate negotiation.
■ In the CPRI parameter editor, set the transceiver to run at the highest CPRI line
rate this device family supports.
■ Include additional external data and logic in your design, such as the following
required data and logic:
■ Input data to the ALTGX_RECONFIG megafunction, or Altera Transceiver
Reconfiguration Controller for Arria V, Cyclone V, and Stratix V devices, for
each CPRI line rate to be checked. Refer to
Figure B–1 and Figure B–2 .
■ Logic to modify the frequency of the usr_pma_clk and usr_clk input clocks in
Arria V GT variations configured with a CPRI line rate of 9.8304 Gbps. Refer to
“Autorate Negotiation From 9.8304 Gbps in Arria V GT Variations” on
page B–4
.
■ In Arria V GX and Arria V GT variations, if autorate negotiation involves a CPRI
line rate of 4915.2 Mbps or higher, you must configure the Transceiver
Reconfiguration Controller to perform duty cycle calibration. Refer to
Dynamic
Reconfiguration in Arria V Devices .
■ For Cyclone IV GX devices, you must implement logic to perform autorate
negotiation by reconfiguring the transceiver directly, using the required
ALTGX_RECONFIG megafunction. Refer to
Figure B–1 and Figure B–2 .
In Cyclone IV GX devices, autorate negotiation is implemented by performing
scan-chain based PLL reconfiguration of the MPLL associated with the relevant
transceiver channel. Designs that target a Cyclone IV GX device therefore require an
ALTPLL_RECONFIG megafunction to perform PLL reconfiguration of the MPLL.