Altera CPRI IP Core - Manual (Page 214)

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Document Revision History
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
February 2013 12.1 SP1
■ Added support for the CPRI V5.0 Specification in “General Description” on page 1–2 and
“CPRI IP Core Features” on page 1–3 . Updated Figure 4–25 on page 4–47 to include
Ctrl_AxC bytes in control word, a new feature in the V5.0 specification. Updated
Chapter 4, Functional Description mentions that features comply with the CPRI
specification, to indicate the V5.0 specification where appropriate. Clarified that the
CPRI IP core MAP interface does not implement the GSM mapping feature of the V5.0
specification. You must implement GSM mapping in communication through the IP core
AUX interface.
■ Added support for Arria V GZ devices at CPRI line rates up through 9.8304 Gbps, with
autorate negotiation support among all of these line rates. (Support for the 9.8304 Gbps
CPRI line rate is new in the 12.1 SP1 release).
■ Added autorate negotiation support for Arria V GT devices to and from CPRI line rate
9.8304 Gbps. Updated
Appendix B, Implementing CPRI Link Autorate Negotiation with
the additional requirements for this case. Arria V GT variations configured with the CPRI
line rate of 9.8304 Gbps cannot negotiate down to a CPRI line rate of 0.6144 Gbps.
(Autorate negotiation support at this CPRI line rate is new in the 12.1 SP1 release).
■ Added support for Cyclone V GX devices at CPRI line rates up through 3.072 Gbps, with
autorate negotiation support among all of these line rates. (Cyclone V GX device support
is new in the 12.1 release).
■ Documented support for new dynamic master–slave clock mode and slave–master
clock mode switching capability in new section
“Dynamically Switching Clock Mode” on
page 4–9 and in update to description of CPRI_CONFIG register (offset 0x8) in
Table 7–6 on page 7–4 .
■ Documented support for new slave IP core self-synchronization feature in new section
“Achieving Link Synchronization Without an REC Master” on page 5–4 and in update to
description of CPRI_CONFIG register (offset 0x8) in Table 7–6 on page 7–4 .
■ Documented new register access method to full CPRI frame control word in updated
“Accessing the Hyperframe Control Words” on page 4–43 and in update to descriptions
of CPRI_CTRL_INDEX register (offset 0xC) in Table 7–7 on page 7–5 , CPRI_RX_CTRL
register (offset 0x10) in Table 7–8 on page 7–6 , and CPRI_TX_CTRL register (offset
0x14) in Table 7–9 on page 7–6 .
■ Updated Chapter 8, Testbenches with new testbench tb_altera_cpri_autorate_98G_phy,
which demonstrates autorate negotiation in Arria V GT devices configured at the CPRI
line rate of 9.8304 Gbps. (This testbench is new in the 12.1 SP1 release).
■ Updated “Running the Testbenches” on page 8–8 to document new testbench flow for
all four Altera-supported simulators.
Continued...
Date Version Changes Made