Fixed rx core delay component” on – Altera CPRI IP Core User Manual
Page 185
Appendix E: Delay Measurement and Calibration
E–7
Single-Hop Delay Measurement
December 2013
Altera Corporation
CPRI MegaCore Function
User Guide
Round-Trip Calibration Delay
The new dynamic pipelining feature for round-trip delay calibration introduces a
delay in the Rx path in an RE slave. In CPRI IP core variations other than the
Arria V GT 9.8 Gbps variations, this delay is introduced to the Rx path
immediately following the Rx elastic buffer. In the Arria V GT 9.8 Gbps
variations, this delay is introduced in the CPRI Rx block. The feature introduces
the new delay to maintain a round-trip delay measurement as close as possible to
the anticipated round-trip delay you provide to the CPRI IP core. The
CPRI_AUTO_CAL
register holds the anticipated delay that you program, an enable
bit you turn on to activate the feature, and a status field in which the CPRI IP core
reports its relative success in maintaining the round-trip delay you requested.
The register also contains a field,
cal_pointer
, that the CPRI IP core updates
dynamically with the current number of
cpri_clkout
cycles of delay that this
feature adds. You must include this register field value in your Rx path delay
calculation. If the enable bit of the
CPRI_AUTO_CAL
register has the value of 0, the
delay is 3
cpri_clkout
cycles.
f
For more information about this feature, refer to
“Dynamic Pipelining for Automatic
Round-Trip Delay Calibration” on page E–19
and to
Fixed Rx Core Delay Component
In the Rx path, the delay from the Rx transceiver to the Rx elastic buffer,
(component 1(b) in
“Most CPRI IP Core Variations” on page E–3
) and the delay
from the CPRI low-level receiver block to the AUX interface or through the MAP
interface block (component 2 in
Figure E–3 on page E–3
and
Figure E–4 on
page E–10
), are fixed. This combined delay depends on the device family and
CPRI data rate. This delay is the fixed delay component of the delay labeled T_R1
in
Figure E–1 on page E–2
.
Table E–3
shows the sum of these two fixed delays in the different device families.