Altera CPRI IP Core - Manual (Page 81)

Chapter 4: Functional Description 4–49
CPU Interface
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
You must write each frame’s data to the ETH_TX_DATA register continuously. The
Ethernet transmitter module ensures the correct bit order for transmission on the
CPRI link. If the
crc_enable field of the ETH_CONFIG_2 register has the value of 0, you
must insert the CRC in the frame data, because the Ethernet receiver module checks
CRC. In this case, you must reverse the bit order of the CRC bytes so that the most
significant byte of the CRC is transmitted first.
1 If you set the crc_enable field of the ETH_CONFIG_2 register to the value of 1, the Tx
Ethernet automatically calculates the Frame check sequence and inserts it at the end of
the Ethernet frame data in the Tx Ethernet buffer.
Software can set the tx_discard bit in the ETH_TX_CONTROL register, which in turn
causes the tx_abort bit in the ETH_TX_STATUS register to be set. The Ethernet
transmitter module can also set the tx_abort bit directly.
The Tx Ethernet controller reads the Tx Ethernet buffer after you set the tx_eop bit of
the ETH_TX_CONTROL register and write the final word in the ETH_TX_DATA register. If
you disable the store-and-forward feature by resetting the tx_st_fwd field of the
ETH_FWD_CONFIG register at offset 0x244 ( Table 7–64 on page 7–27 ), the Tx Ethernet
controller also reads the Tx Ethernet buffer whenever the number of words in the Tx
Ethernet buffer is above a programmable threshold.
Interrupts
Software can enable interrupts by setting bits in the ETH_CONFIG_1 register at offset
0x208 ( Table 7–53 on page 7–24 ). The intr_en bit is the Ethernet global interrupt
enable and intr_tx_en is the Ethernet Tx interrupt enable. If both of these two bits are
set, software can use the status in the ETH_TX_STATUS register to generate interrupts.
For example, using the tx_ready_block bit to generate an interrupt ensures that the
CPU is interrupted only when a full 32-bit packet of data is ready to transfer to the
Ethernet Tx buffer.
Receiving Ethernet Traffic
The Ethernet receiver module receives Ethernet data from the CPRI link by reading it
from the Ethernet Rx buffer through an Ethernet register.
This section describes how the Ethernet receiver module performs MAC address
filtering according to the
ETH_CONFIG_1 , ETH_ADDR_LSB , and ETH_ADDR_MSB registers,
provides status information to the CPU interface in the ETH_RX_STATUS register, and
allows the CPU interface to insert wait states in the Ethernet channel.
For additional information about the Ethernet receiver registers, refer to Chapter 7,
Software Interface .
MAC Address Filtering
To enable MAC address checking, set the mac_check bit of the ETH_CONFIG_1 register.
If the mac_check bit is reset to the value of zero, the Ethernet receiver accepts all
received packets.
You can enable the following three MAC address filters:
■ Unicast filtering: check that the destination MAC address is the address specified
in the
ETH_ADDR_LSB and ETH_ADDR_MSB registers. If the mac_check bit is not set, this
filter is disabled.