Altera CPRI IP Core - Manual (Page 179)

December 2013 Altera Corporation CPRI MegaCore Function
User Guide
E. Delay Measurement and Calibration
This appendix describes the delay measurement and calibration features of the CPRI
IP core.
1 The latency numbers given in this section are for the Quartus II software version 13.1.
Delay Measurement and Calibration Features
For system configuration and correct synchronization, the CPRI IP core must meet the
CPRI V5.0 Specification measurement and delay requirements. The CPRI IP core
provides the following support for accurate delay measurement:
■ Provides current Rx delay measurement values in the CPRI_RX_DELAY and
CPRI_EX_DELAY_STATUS delay registers.
■ Provides current Tx delay calibration values in the CPRI_TX_BITSLIP register.
■ Provides current round-trip delay value in the CPRI_ROUND_DELAY register.
■ Supports user control over delay measurement accuracy by the following
methods:
■ Allows you to control the degree of delay accuracy in the status registers by
programming the
CPRI_RX_DELAY_CTRL and CPRI_EX_DELAY_CONFIG registers.
■ Provides an optional automatic calibration process that takes your input for the
desired round-trip delay and adjusts internal delays in an attempt to match the
desired value. The automatic calibration process reports its current success
status in the
CPRI_AUTO_CAL register.
The following sections describe the delay requirements and how you can use these
registers to ensure that your application conforms to the CPRI V5.0 Specification
delay requirements.
Delay Requirements
CPRI V5.0 Specification requirements R-17, R-18, and R-18A address jitter and
frequency accuracy in the RE core clock for radio transmission. The relevant clock
synchronization is performed using an external clean-up PLL that is not included in
the CPRI IP core.
The CPRI IP core complies with CPRI V5.0 Specification requirements R-19, R-20,
R-20A, R-21, and R-21A.
CPRI V5.0 Specification requirement R-20A addresses the maximum allowed delay in
switching between receiving and transmitting on the AxC interface. Because the CPRI
IP core provides duplex communication on the AxC interfaces, this switch requires
only the programming of the relevant AxC interface Tx or Rx enable bit in the
CPRI_IQ_TX_BUF_CONTROL or CPRI_IQ_RX_BUF_CONTROL register, and no delay calculation
is required.