Altera CPRI IP Core - Manual (Page 77)

Chapter 4: Functional Description 4–45
CPU Interface
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
4. If the CPRI line rate is greater than 2.4576 Gbps, increment the
cpri_ctrl_position field of the CPRI_CTRL_INDEX register to the value of 1 and
write the second 32-bit section of the next intended #Z.X control word to the
CPRI_TX_CTRL register.
5. If the CPRI line rate is greater than 4.9152 Gbps, increment the
cpri_ctrl_position field of the CPRI_CTRL_INDEX register to the value of 2 and
write the third 32-bit section of the next intended #Z.X control word to the
CPRI_TX_CTRL register.
6. If the CPRI line rate is 9.8304 Gbps, increment the cpri_ctrl_position field of the
CPRI_CTRL_INDEX register to the value of 3 and write the fourth 32-bit section of the
next intended #Z.X control word to the CPRI_TX_CTRL register.
7. Set the tx_control_insert bit in the CPRI_CTRL_INDEX register to the value of one.
8. After you update the control transmit table, set the tx_ctrl_insert_en bit of the
CPRI_CONFIG register to enable the CPRI IP core to write the values from the
control transmit table to the control words in the outgoing CPRI frame.
The tx_control_insert bit of the CPRI_CTRL_INDEX register enables or disables the
transmission of the corresponding control transmit table entry in the CPRI frame. The
tx_ctrl_insert_en bit of the CPRI_CONFIG register is the master enable: when it is set,
the CPRI IP core writes all table entries with the tx_control_insert bit set into the
CPRI frame.