Rainbow Electronics W90P710CDG - Manual (Page 11)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 11 - Revision B2
y When reach middle and end address of destination address, a DMA_IRQ is requested to CPU
automatically
Smart Card Host Interface (SCHI)
y ISO-7816 compliant
y PC/SC T=0, T=1 compliant
y 16-byte transmitter FIFO and 16-byte receiver FIFO
y FIFO threshold interrupt to optimize system performance
y Programmable transmission clock frequency
y Versatile baud rate configuration
y UART-like register file structure
y General-purpose C4, C8 channels
SD Host Interface
y
Directly connect to Secure Digital (SD, MMC) flash memory card.
y Supports DMA function to accelerate the data transfer between the internal buffer, external
SDRAM, and flash memory card.
y Two 512 bytes internal buffers are embedded inside the controller.
y No SPI mode.
KeyPad Scan Interface
y
Scan up to 16 rows by 8 columns with an external 4 to 16 decoder and 4 rows by 8 columns array
without auxiliary component
y Programmable debounce time
y One or two keys scan with interrupt and three keys reset function.
y Wakeup CPU from IDEL/Power Down mode
PS2 Host Interface
y
APB slave consisted of PS2 protocol.
y Connect IBM keyboard or bar-code reader through PS2 interface.
y Provide hardware scan code to ASCII translation
Power management
y
Programmable clock enables for individual peripheral
y IDLE mode to halt ARM Core and keep peripheral working
y Power-Down mode to stop all clocks included external crystal oscillator.
y Exit IDLE by all interrupts
y Exit Power-Down by keypad,USB device and external interrupts