Rainbow Electronics W90P710CDG - Manual (Page 45)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 45 - Revision B2
Table 6.2.13 and Table 6.2.14
Using little-endian and byte access, Program/Data path between register and external memory.
BA = Address whose LSB is 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
BAL = Address whose LSB is 0,2,4,6,8,A,C,E
BAU = Address whose LSB is 1,3,5,7,9,B,D,F
BA0 = Address whose LSB is 0,4,8,C BA1 = Address whose LSB is 1,5,9,D
BA2 = Address whose LSB is 2,6,A,E BA3 = Address whose LSB is 3,7,B,F
Table6.2.13 Byte access write operation with little Endian
Access Operation Write Operation (CPU Register Î External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD 31 0
ABCD 31 0
ABCD
SA BA0 BA1 BA2 BA3 BAL BAU BA
Bit Number
SD
31 0
D D D D
31 0
D D D D
31 0
D D D D
31 0
D D D D
31 0
D D D D
31 0
D D D D
31 0
D D D D
Bit Number
ED
7 0
D
15 8
D
23 16
D
31 24
D
7 0
D
15 8
D
7 0
D
XA BA0 BA0 BA0 BA0 BAL BAL BA
nWBE [3-0] /
SDQM [3-0]
UUUA UUAU UAUU AUUU XXUA XXAU XXXA
Bit Number
XD
31 0
X X X D
31 0
X X D X
31 0
X D X X
31 0
D X X X
15 0
X D
15 0
D X
7 0
D
Bit Number
Ext. Mem Data
7 0
D
15 8
D
23 16
D
31 24
D
7 0
D
15 8
D
7 0
D
Timing Sequence
Table6.2.14 Byte access read operation with Little Endian
Access Operation Read Operation (CPU Register Í External Memory)
XD Width Word Half Word Byte
Bit Number
CPU Reg Data
7 0
D
7 0
C
7 0
B
7 0
A
7 0
D
7 0
C
7 0
D
SA BA0 BA1 BA2 BA3 BAL BAU BA
Bit Number
SD
7 0
D
7 0
C
7 0
B
7 0
A
7 0
D
7 0
C
7 0
D
Bit Number
ED
7 0
D
7 0
C
7 0
B
7 0
A
7 0
D
7 0
C
7 0
D
XA BA0 BA0 BA0 BA0 BAL BAL BA
SDQM [3-0] UUUA UUAU UAUU AUUU XXUA XXAU XXXA
Bit Number
XD
31 0
ABCD 31 0
ABCD 31 0
ABCD 31 0
ABCD 15 0
CD
15 0
CD
7 0
D
Bit Number
Ext. Mem Data
31 0
ABCD 15 0
CD
7 0
D
Timing Sequence