Rainbow Electronics W90P710CDG - Manual (Page 358)

W90P710CD/W90P710CDG
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HSUART Line Control Register (HSUART_LCR)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
HSUART_LCR 0x0C R/W Line Control Register 0x0000_0000
BITS DESCRIPTIONS
[31:8] Reserved -
[7] DLAB
Divider Latch Access Bit
0 = It is used to access RBR, THR or IER.
1 = It is used to access Divisor Latch Registers {DLL, DLM}.
[6] BCB
Break Control Bit
When this bit is set to logic 1, the serial data output (SOUT) is
forced to the Spacing State (logic 0). This bit acts only on
SOUT and has no effect on the transmitter logic.
[5] SPE
Stick Parity Enable
0 = Disable stick parity
1 = Parity bit is transmitted and checked as a logic 1 if bit 4 is
0 (odd parity), or as a logic 0 if bit 4 is 1 (even parity). This
bit has effect only when bit 3 (parity bit enable) is set.
[4] EPE
Even Parity Enable
0 = Odd number of logic 1’s are transmitted or checked in
the data word and parity bits.
1 = Even number of logic 1’s are transmitted or checked in
the data word and parity bits.
This bit has effect only when bit 3 (parity bit enable) is set.
[3] PBE
Parity Bit Enable
0 = Parity bit is not generated (transmit data) or checked
(receive data) during transfer.
1 = Parity bit is generated or checked between the "last data
word bit" and "stop bit" of the serial data.
[2] NSB
Number of “STOP bit”
0= One “ STOP bit” is generated in the transmitted data
1= One and a half “ STOP bit” is generated in the transmitted
data when 5-bit word length is selected;
Two “ STOP bit” is generated when 6-, 7- and 8-bit word length
is selected.
[1:0] WLS
Word Length Select
WLS[1:0] Character length
00 5 bits
01 6 bits
10
7 bits
11 8 bits