Rainbow Electronics W90P710CDG User Manual
Page 138
W90P710CD/W90P710CDG
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Continued.
BITS
DESCRIPTIONS
[0] EnRXINTR
The Enable Receive Interrupt controls the Rx interrupt generation.
If EnRXINTR is enabled and RXINTR of MISTA register is high, EMC
generates the Rx interrupt to CPU. If EnRXINTR is disabled, no Rx
interrupt is generated to CPU even the status bits 1~14 of MISTA are
set and the corresponding bits of MIEN are enabled. In other words, if
S/W wants to receive Rx interrupt from EMC, this bit must be enabled.
And, if S/W doesn’t want to receive any Rx interrupt from EMC,
disables this bit.
1’b0: RXINTR of MISTA register is masked and Rx interrupt generation
is disabled.
1’b1: RXINTR of MISTA register is unmasked and Rx interrupt
generation is enabled.
MAC Interrupt Status Register (MISTA)
The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO
status and also NATA processing status. The statuses kept in MISTA will trigger the reception or
transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the
status and also clears the interrupt.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MISTA
0xFFF0_30B0 R/W
MAC Interrupt Status Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved TxBErr
23
22
21
20
19
18
17
16
TDU LC
TXABT
NCS
EXDEF
TXCP
TXEMP
TXINTR
15
14
13
12
11
10
9
8
Reserved
CFR Reserved RxBErr
RDU
DENI DFOI
7
6
5
4
3
2
1
0
MMP RP
ALIE
RXGD
PTLE RXOV CRCE RXINTR