Rainbow Electronics W90P710CDG User Manual
Page 384
W90P710CD/W90P710CDG
- 384 -
The AIC classifies the interrupt into FIQ and IRQ. This register indicates whether the asserted
interrupt is FIQ or IRQ. If both IRQ and FIQ are equal to 0, it means there is no interrupt occurred.
BITS
DESCRIPTIONS
[31:2]
Reserved
Reserved
[1]
IRQ
IRQ [1]: Interrupt Request
0 = nIRQ line is inactive.
1 = nIRQ line is active.
[0]
FIQ
FIQ [0]: Fast Interrupt Request
0 = nFIQ line is inactive.
1 = nFIQ line is active
AIC Mask Enable Command Register (AIC_MECR)
REGISTER ADDRESS R/W
DESCRIPTION
RESET
VALUE
AIC_MECR 0xFFF8_2120
W
Mask Enable Command Register
Undefined
31
30
29
28
27
26
25
24
MEC31 MEC30 MEC29 MEC28
MEC27 MEC26 MEC25 MEC24
23
22
21
20
19
18
17
16
MEC23 MEC22 MEC21 MEC20 MEC19 MEC18 MEC17 MEC16
15
14
13
12
11
10
9
8
MEC15 MEC14 MEC13 MEC12 MEC11 MEC10 MEC9 MEC8
7
6
5
4
3
2
1
0
MEC7 MEC6 MEC5 MEC4 MEC3 MEC2 MEC1
RESERVED
BITS
DESCRIPTIONS
[31:1]
MEC
x
MEC x: Mask Enable Command
0 = No effect
1 = Enables the corresponding interrupt channel
[0]
Reserved
Reserved