Rainbow Electronics W90P710CDG User Manual
Page 243
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 243 -
Revision B2
SD BIST Register (SDBIST)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
SDBIST
0xFFF0_7014
R/W
SD BIST Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved BistFail
Finish
BISTEN
BITS
DESCRIPTIONS
[31:4]
Reserved -
[3:2]
BistFail
BIST Fail
The BistFail indicates if the BIST test fails or succeeds. If the BistFail is
low at the end, the embedded SRAM pass the BIST test, otherwise, it is
faulty. The BistFail will be high once the BIST detects the error and
remains high during the BIST operation.
The BistFail is a write clear field. Write 1 to this field clears the content
and write 0 has no effect.
[1]
Finish
BIST Operation Finish
It indicates the end of the BIST operation. When BIST controller finishes
all operations, this bit will be set high.
This bit is a write clear field. Write 1 to this field clears the content and
write 0 has no effect.
[0]
BISTEN
BIST Enable
The BISTEN is used to enable the BIST operation. If high enables the
BIST controller to do embedded SRAM test. This bit is also used to do
the reset for BIST circuit. It is necessary to reset the BIST circuit one
clock cycle at least in order to initialize the BIST properly.
The BISTEN can be disabled by write 0.