Rainbow Electronics W90P710CDG - Manual (Page 81)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 81 - Revision B2
Continued.
BITS DESCRIPTION
[7:5] tACS
Address set-up before nECS for external I/O bank 0~3
tACS [7:5] MCLK
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
[4:2] tCOS
Chip selection set-up time of external I/O bank 0~3
When ROM/Flash memory bank is configured, the access to its bank
stretches chip selection time before the nOE or new signal is activated.
tCOS [4:2] MCLK
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
[1:0] DBWD
Programmable data bus width for external I/O bank 0~3
DBWD [1:0] Width of Data Bus
0 0 Disable bus
0 1 8-bit
1 0 16-bit
1 1 32-bit