Rainbow Electronics W90P710CDG User Manual
Page 93
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 93 -
Revision B2
REGISTER ADDRESS R/W
DESCRIPTION
RESET
VALUE
CAHCON
0xFFF0_2004
R/W Cache control register
0x0000_0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
DRWB ULKS ULKA LDLK FLHS FLHA DCAH ICAH
BITS
DESCRIPTION
[31:8] RESERVED
-
[7] DRWB
Drain write buffer
Forces write buffer data to be written to main memory.
[6] ULKS
Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in
CAHADR register must be specified.
[5] ULKA
Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared
to 0.
[4] LDLK
Load and Lock I-Cache/D-Cache
Loads the instruction or data from external memory and locks into
cache. Both WAY and ADDR bits in CAHADR register must be
specified.
[3] FLHS
Flush I-Cache/D-Cache single line
Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR
bits in CAHADR register must be specified.
[2] FLHA
Flush I-Cache/D-Cache entirely
To flush the entire I-Cache/D-Cache, also flushes any locked-down
code. If the I-Cache/D-Cache contains locked down code, the
programmer must flush lines individually
[1] DCAH
D-Cache selected
When set to “1”, the command set is executed with D-Cache.
[0] ICAH
I-Cache selected
When set to “1”, the command set is executed with I-Cache.