Rainbow Electronics W90P710CDG User Manual
Page 159
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 159 -
Revision B2
Debug Mode MAC Information Register (DMMIR)
The DMMIR keeps the information of MAC module for debug.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
DMMIR
0xFFF0_3214
R
Debug Mode MAC Information Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
RBC
7
6
5
4
3
2
1
0
RBC
BITS
DESCRIPTIONS
[31:16] Reserved
-
[15:0]
RBC
Receive Byte Count
BIST Mode Register (BISTR)
The BISTR controls the BIST (Built In Self Test) for embedded SRAM, 256B for RxFIFO and 256B for
TxFIFO.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
BISTR
0xFFF0_3300
R/W
BIST Mode Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved BistFail
Finish
BMEn