Rainbow Electronics W90P710CDG - Manual (Page 344)

W90P710CD/W90P710CDG
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BITS DESCRIPTIONS
[7:6] RFITL
RX FIFO Interrupt (Irpt_RDA) Trigger Level
RFITL [7:6] Irpt_RDA Trigger Level (Bytes)
00 01
01 04
10 08
11 14
[3] DMS
DMA Mode Select
The DMA function is not implemented in this version.
[2] TFR
TX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset TX FIFO. The
TX FIFO becomes empty (TX pointer is reset to 0) after such reset. This bit is
returned to 0 automatically after the reset pulse is generated.
[1] RFR
RX FIFO Reset
Setting this bit will generate an OSC cycle reset pulse to reset RX FIFO. The
RX FIFO becomes empty (RX pointer is reset to 0) after such reset. This bit
is returned to 0 automatically after the reset pulse is generated.
[0] FME
FIFO Mode Enable
Because UART is always operating in the FIFO mode, writing this bit has no
effect while reading always gets logical one. This bit must be 1 when other
FCR bits are written to; otherwise, they will not be programmed.
UART Line Control Register (UART_LCR)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
UART_LCR 0x0C R/W Line Control Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
DLAB BCB SPE EPE PBE NSB WLS