Rainbow Electronics W90P710CDG User Manual
Page 486
W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 487 -
Revision B2
USI Divider Register (USI_DIVIDER)
REGISTER ADDRESS R/W
DESCRIPTION
RESET
VALUE
USI_Divider
0xFFF8_6204
R/W
USI Clock Divider Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
DIVIDER[15:8]
7
6
5
4
3
2
1
0
DIVIDER[7:0]
BITS
DESCRIPTIONS
[15:0]
DIVIDER
Clock Divider Register
The value in this field is the frequency divider of the system clock pclk
to generate the serial clock on the output usi_sclk_o. The desired
frequency is obtained according to the following equation:
(
)
2
*
1
+
=
DIVIDER
f
f
pclk
sclk
NOTE: Suggest DIVIDER should be at least 1.
USI Slave Select Register (USI_SSR)
REGISTER ADDRESS R/W
DESCRIPTION
RESET
VALUE
USI_SSR
0xFFF8_6208
R/W
USI Slave Select Register
0x0000_0000