Rainbow Electronics W90P710CDG User Manual
Page 214
W90P710CD/W90P710CDG
- 214 -
BITS
DESCRIPTIONS
[31:6]
Reserved
[6]
EPA_ZERO
Send zero length packet to HOST
[5]
EPA_STL_CLR
CLEAR the Endpoint A stall(WRITE ONLY)
[4]
EPA_THRE
Endpoint A threshold (only for ISO)
1: once available space in FIFO over 16 bytes, DMA accesses
memory
0: once available space in FIFO over 32 bytes, DMA accesses
memory
[3]
EPA_STL
Set the Endpoint A stall
[2]
EPA_RDY
The memory is ready for Endpoint A to access
[1]
EPA_RST
Endpoint A reset
[0]
EPA_EN
Endpoint A enable
USB Endpoint A interrupt enable Register (EPA_IE)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
EPA_IE
0xFFF06050
R/W
USB endpoint A Interrupt Enable register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
Reserved EPA_CF_IE
EPA_BUS_ERR_IE
EPA_DMA_IE
EPA_ALT_IE
EPA_TK_IE EPA_STL_IE