Rainbow Electronics W90P710CDG - Manual (Page 127)

W90P710CD/W90P710CDG
Publication Release Date: September 19, 2006
- 127 - Revision B2
BITS DESCRIPTIONS
[31:24] Reserved -
[23:20] MDCCR
The MDC Clock Rating controls the MDC clock rating for MII
Management I/F.
Depend on the IEEE Std. 802.3 clause 22.2.2.11, the minimum
period for MDC shall be 400ns. In other words, the maximum
frequency for MDC is 2.5MHz. The MDC is divided from the AHB bus
clock, the HCLK. Consequently, for different HCLKs the different
ratios are required to generate appropriate MDC clock.
The following table shows relationship between HCLK and MDC
clock in different MDCCR configurations. The T
HCLK
indicates the
period of HCLK.
[19] MDC
The MDC Clock ON Always controls the MDC clock generation. If the
MDCON is set to high, the MDC clock actives always. Otherwise, the
MDC will only active while S/W issues a MII management command.
1’b0: The MDC clock will only active while S/W issues a MII
management command.
1’b1: The MDC clock actives always.
[18] PreSP
The Preamble Suppress controls the preamble field generation of
MII management frame. If the PreSP is set to high, the preamble field
generation of MII management frame is skipped.
1’b0: Preamble field generation of MII management frame is not
skipped.
1’b1: Preamble field generation of MII management frame is skipped.
[17] BUSY
The Busy Bit controls the enable of the MII management frame
generation. If S/W wants to access registers of external PHY, it set
BUSY to high and EMC generates the MII management frame to
external PHY through MII Management I/F.
The BUSY is a self-clear bit. This means the BUSY will be cleared
automatically after the MII management command finished.
1’b0: The MII management has finished.
1’b1: Enable EMC to generate a MII management command to
external PHY.
[16] Write
The Write Command defines the MII management command is a
read or write.
1’b0: The MII management command is a read command.
1’b1: The MII management command is a write command.
[15:13] Reserved