Figure 7.35: ladder diagram for falling edge, Figure 7.35:ladder diagram for falling edge – B&B Electronics ADAM-6066 - Manual User Manual

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ADAM-6000 Series User Manual

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You can see the DO 0 will only be triggered when falling edge of DI 0
occurs. In the example project we provide, the DO status will remain
logic high for 1 second. Then it will back to logic low. When PLC is used
for this kind of application, the ladder diagram will look similar to Figure
7.35 below:

Figure 7.35: Ladder Diagram for Falling Edge

When you use GCL to achieve falling edge application, 3 logic rules, 1
Internal Timer (Timer 0) and 1 Internal Flag (Flag 0) are needed. Please
refer to Figure 7.36 below for GCL logic architecture. With logic rule 3,
DO 0 value is controlled by DI 0 and Flag 0. Flag 0 value is logic False at
beginning.

When falling edge occurs (DI value changes from logic high to logic
low), DO will be activated (logic rule 3 are satisfied), and Timer 0 starts
to count time (logic rule 1 are satisfied). After Timer 0 counts up to the
specific time interval (1 second), Flag 0 will become logic True by logic
rule 2, making DO 0 value logic low (logic rule 3 are not satisfied). The
GCL architecture is similar to the ladder diagram.

( )

T0

[ ]

T0 ≧ 1

( )

DI 0

( )

Flag0

DO 0

DI 0

Flag0

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