ARM Cortex R4F - Manual (Page 103)

System Control Coprocessor
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Table 4-7 shows how the bit values correspond with the Processor Feature Register 0 functions.
To access the Processor Feature Register 0 read CP15 with:
MRC p15, 0, <Rd>, c0, c1, 0 ; Read Processor Feature Register 0
c0, Processor Feature Register 1, PFR1
The Processor Feature Register 1 provides information about the execution state support and
programmer’s model for the processor.
Processor Feature Register 1 is:
•
a read-only register
• accessible in Privileged mode only.
Figure 4-13 shows the bit arrangement for Processor Feature Register 1.
Figure 4-13 Processor Feature Register 1 format
Table 4-8 shows how the bit values correspond with the Processor Feature Register 1 functions.
Table 4-7 Processor Feature Register 0 bit functions
Bits Field Function
[31:16] Reserved SBZ.
[15:12] State3 Indicates support for Thumb Execution Environment (ThumbEE).
0x0 , no support.
[11:8] State2 Indicates support for acceleration of execution environments in hardware or software.
0x1 , the processor supports acceleration of execution environments in software.
[7:4] State1 Indicates type of Thumb encoding that the processor supports.
0x3 , the processor supports Thumb encoding with all Thumb instructions.
[3:0] State0 Indicates support for ARM instruction set.
0x1
, the processor supports ARM instructions.
31 12 11 8 7 4 3 0
Reserved
Microcontroller programmer’s model
Security extension
ARMv4 Programmer’s model
Table 4-8 Processor Feature Register 1 bit functions
Bits Field Function
[31:12] Reserved SBZ.