ARM Cortex R4F - Manual (Page 387)

Cycle Timings and Interlock Behavior
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 14-23
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PUSH {R1-R7}
ADD R10,R10,R7
Note
In the examples, R0 and
sp
are 64-bit aligned addresses. The instructions
PUSH
and
POP
always
use the
sp
register for the base address.