ARM Cortex R4F - Manual (Page 228)

Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-32
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The following code is an example of disabling the caches:
MRC p15, 0, R1, c1, c0, 0 ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<12 ; instruction cache disable
BIC R1, R1, #0x1 <<2 ; data cache disable
DSB
MCR p15, 0, R1, c1, c0, 0
; disabled cache RAMs
ISB
; Clean entire data cache. This routine will depend on the data cache size. It can be
omitted if it is known that the data cache has no dirty data
Disabling or enabling instruction cache
The following code is an example of enabling the instruction cache:
MRC p15, 0, R1, c1, c0, 0 ; Read System Control Register configuration data
ORR R1, R1, #0x1 <<12 ; instruction cache enable
MCR p15, 0, r0, c7, c5, 0 ; Invalidate entire instruction cache
MCR p15, 0, R1, c1, c0, 0 ; enabled instruction cache
ISB
The following code is an example of disabling the instruction cache:
MRC p15, 0, R1, c1, c0, 0 ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<12 ; instruction cache enable
MCR p15, 0, R1, c1, c0, 0 ; disabled instruction cache
ISB
Disabling or enabling data cache
The following code is an example of enabling the data cache:
MRC p15, 0, R1, c1, c0, 0 ; Read System Control Register configuration data
ORR R1, R1, #0x1 <<2
DSB
MCR p15, 0, r0, c15, c5, 0 ; Invalidate entire data cache
MCR p15, 0, R1, c1, c0, 0
; enabled data cache
The following code is an example of disabling the cache RAMs:
MRC p15, 0, R1, c1, c0, 0 ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<2
DSB
MCR p15, 0, R1, c1, c0, 0
; disabled data cache
; Clean entire data cache. This routine will depend on the data cache size. It can be
omitted if it is known that the data cache has no dirty data.
Disabling or enabling error checking
Software must take care when changing the error checking bits in the Auxiliary Control
Register. If the bits are changed when the caches contain data, the parity or ECC bits in the
caches might not be correct for the new setting, resulting in unexpected errors and data loss.
Therefore the bits in the Auxiliary Control Register must only be changed when both caches are
turned off and the entire cache must be invalidated after the change.
The following code is the recommended sequence to perform the change:
MRC p15, 0, r0, c1, c0, 0 ; Read System Control Register
BIC r0, r0, #0x1 << 2
; Disable data cache bit
BIC r0, r0, #0x1 << 12 ; Disable instruction cache bit
DSB
MCR p15, 0, r0, c1, c0, 0 ; Write System Control Register
ISB ; Ensures following instructions are not executed from cache