6 accessing rams using the axi slave interface, Accessing rams using the axi slave interface -24, Table 9-26 – ARM Cortex R4F User Manual
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Level Two Interface
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9.6
Accessing RAMs using the AXI slave interface
This section describes how to access the TCM and cache RAMs using the AXI slave interface.
Table 9-26 shows the bits of the ARUSERS or AWUSERS inputs to use to access RAM or a
group of RAMs. Each bit is a one-hot 4-bit input, with each bit corresponding to a particular
RAM or group of RAMs.
For the caches and the BTCMs, more decoding is performed depending on the address of the
request, ARADDRS for reads and AWADDRS for writes. For more information see:
•
•
Cache RAM access on page 9-26.
Note
Because AWUSERS and AWADDRS work in the same way as ARUSERS and ARADDRS,
the following sections only describe ARUSERS and ARADDRS.
Table 9-26 RAM region decode
AxUSERS bit
One-hot RAM select
[3]
Data cache RAMs
[2]
Instruction cache RAMs
[1]
B0TCM and B1TCM
[0]
ATCM