ARM Cortex R4F - Manual (Page 94)

System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-10
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c8-c15 0-7 Undefined - - -
1 c0 0 Current Cache Size ID Read-only - cd page 4-32
1 Current Cache Level ID Read-only
0x09000003
c page 4-34
2-7 Undefined - - -
c1-c15 0-7
2 c0 0 Cache Size Selection Read/write Unpredictable page 4-35
c1 0 c0 0 System Control Read/write - d page 4-35
1 Auxiliary Control Read/write - d page 4-38
2 Coprocessor Access Read/write
0x00000000
page 4-44
3-7 Undefined - - -
c1-c15 0-7
c2-c4 0 c0-c15 0-7
c5 0 c0 0 Data Fault Status Read/write Unpredictable page 4-45
1 Instruction Fault Status Read/write Unpredictable page 4-46
2-7 Undefined - - -
c1 0 Auxiliary Data Fault Status Read/write Unpredictable page 4-47
c5 0 c1 1 Auxiliary Instruction Fault
Status Read/write Unpredictable page 4-47
2-7 Undefined - - -
c2-c15 0-7
c6 0 c0 0 Data Fault Address Read/write Unpredictable page 4-48
1 Undefined - - -
2 Instruction Fault Address Read/write Unpredictable page 4-49
3-7 Undefined - - -
c1 0 MPU Region Base Address Read/write 0x00000000 page 4-50
1 Undefined - - -
2 MPU Region Size and
Enable Read/write 0x00000000 page 4-50
3 Undefined - - -
4 MPU Region Access
Control Read/write
0x00000000
page 4-51
5-7 Undefined - - -
c2 0 MPU Memory Region
Number Read/write 0x00000000 page 4-53
Table 4-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation Type Reset value Page