ARM Cortex R4F - Manual (Page 95)

System Control Coprocessor
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 4-11
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1-7 Undefined - - -
c3-c15 1-7
c7 0 c0 0-3 Undefined - - -
4 NOP, previously Wait For
Interrupt Write-only - page 4-54
5-7 Undefined - - -
c1-c4 0-7
c5 0 Invalidate entire instruction
cache Write-only - page 4-55
c7 0 c5 1 Invalidate instruction cache
line by address to
Point-of-Unification. Write-only - page 4-55
2-3 Undefined - - -
4 Flush prefetch buffer Write-only - page 4-55
5 Undefined - - -
6 Invalidate entire branch
predictor array Write-only - page 4-55
7 Invalidate address from
branch predictor array Write-only - page 4-55
c6 0 Undefined - - -
1 Invalidate data cache line
by physical address Write-only - page 4-55
2 Invalidate data cache line
by Set/Way Write-only - page 4-55
3-7 Undefined - - -
c7-9 0-7
c10 0
1 Clean data cache line by
physical address Write-only - page 4-55
2 Clean data cache line by
Set/Way Write-only - page 4-55
3 Undefined - - -
4 Data Synchronization
Barrier Write-only - page 4-57
5 Data Memory Barrier Write-only - page 4-57
6-7 Undefined - - -
c11 0
Table 4-2 Summary of CP15 registers and operations (continued)
CRn Op1 CRm Op2 Register or operation Type Reset value Page