ARM Cortex R4F - Manual (Page 419)

Processor Signal Descriptions
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. A-6
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ERRENRAM[2:0] Input Tie-off,
Reset TCMs external error enable. Tie each bit high to enable the
external error signals for each TCM at reset. Use the following
values:
2: B1TCM
1: B0TCM
0: ATCM
See Auxiliary Control Registers on page 4-38 for more
information.
RMWENRAM[1:0] b Input Tie-off,
Reset RMW enable bits reset values. Tie each bit high to enable
read-modify-write for TCM interfaces at reset.
c Use the
following values:
1: BTCM
0: ATCM
See Auxiliary Control Registers on page 4-38 for more
information.
SLBTCMSB Input Tie-off Use most significant bit of BTCM address to select B1TCM if
this signal is HIGH.
Use bit [3] of the BTCM address if this signal is LOW.
a. If the BTCM is configured with ECC, bit[2] and bit[1] must be the same value.
b. Not used if 32-bit ECC is included.
c. Not available in r0px revisions of the processor.
Table A-2 Configuration signals (continued)
Signal Direction Clocking Description