ARM Cortex R4F - Manual (Page 208)

Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-12
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When the processor is in debug halt-state, any correctable error is corrected as appropriate, but
the memory access is not repeated to fetch the correct data, therefore the instruction generating
the error does not complete successfully. Instead, the sticky precise abort flag in the DSCR is
set. See CP14 c1, Debug Status and Control Register on page 11-14.