ARM Cortex R4F - Manual (Page 133)

System Control Coprocessor
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The Data Fault Address Register bits [31:0] contain the address where the precise abort
occurred.
To access the DFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 0 ; Read Data Fault Address Register
MCR p15, 0, <Rd>, c6, c0, 0 ; Write Data Fault Address Register
A write to this register sets the DFAR to the value of the data written. This is useful for a
debugger to restore the value of the DFAR.
The processor also updates the DFAR on debug exception entry because of watchpoints. See
Effect of debug exceptions on CP15 registers and WFAR on page 11-42 for more information.
c6, Instruction Fault Address Register
The purpose of the Instruction Fault Address Register (IFAR) is to hold the address of
instructions that cause a prefetch abort.
The IFAR is:
•
a read/write register
• accessible in Privileged mode only.
The Instruction Fault Address Register bits [31:0] contain the Instruction Fault address.
To access the IFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 2 ; Read Instruction Fault Address Register
MCR p15, 0, <Rd>, c6, c0, 2 ; Write Instruction Fault Address Register
A write to this register sets the IFAR to the value of the data written. This is useful for a
debugger to restore the value of the IFAR.
4.2.19 c6, MPU memory region programming registers
The MPU memory region programming registers program the MPU regions.
There is one register that specifies which one of the sets of region registers is to be accessed.
See c6, MPU Memory Region Number Register on page 4-53. Each region has its own register
to specify:
•
region base address
• region size and enable
• region access control.
You can implement the processor with eight or 12 regions, or without an MPU entirely. If you
implement the processor without an MPU, then there are no regions and no region programming
registers.
Note
• When the MPU is enabled:
—
The MPU determines the access permissions for all accesses to memory, including
the TCMs. Therefore, you must ensure that the memory regions in the MPU are
programmed to cover the complete TCM address space with the appropriate access
permissions. You must define at least one of the regions in the MPU.
— An access to an undefined area of memory generates a background fault.
• For the TCM space the processor uses the access permissions but ignores the region
attributes from MPU.