ARM Cortex R4F - Manual (Page 220)

Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-24
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• Invalidate data cache by set/way
• Clean data cache by address
• Clean data cache by set/way on page 8-25
• Clean and invalidate data cache by address on page 8-25
• Clean and invalidate data cache by set/way on page 8-25.
Invalidate all instruction cache
This operation ignores all errors in the cache and sets all instruction cache entries to invalid
regardless of error events. This operation cannot generate an imprecise abort, and no error
events are signaled.
Invalidate all data cache
This operation ignores all errors in the cache and sets all data cache entries to invalid regardless
of errors. This operation cannot generate an imprecise abort and no error events are signaled.
Invalidate instruction cache by address
This operation requires a cache lookup. Any errors found in the set that was looked up are fixed
by invalidating that line and, if the address in question is found in the set, it is invalidated.
This operation cannot generate an imprecise abort. Any detected error is signaled with the
appropriate event.
Invalidate data cache by address
This operation requires a cache lookup. Any correctable errors found in the set that was looked
up are fixed and, if the address in question is found in the set, it is invalidated.
Any uncorrectable errors cause an imprecise abort. An imprecise abort can also be raised on a
correctable error if aborts on RAM errors are enabled in the Auxiliary Control Register.
Any detected error is signaled with the appropriate event.
Invalidate data cache by set/way
This operation does not require a cache lookup. It refers to a particular cache line.
The entry at the given set/way is marked as invalid regardless of any errors. This operation
cannot generate an imprecise abort. Any detected error is signaled with the appropriate event.
Clean data cache by address
This operation requires a cache lookup. Any correctable errors found in the set that was looked
up are fixed and, if the address in question is found in the set, the instruction carries on with the
clean operation. When the tag lookup is done, the dirty RAM is checked.
Note
When force write-through is enabled, the dirty bit is ignored.
If the tag or dirty RAM has an uncorrectable error, the data is not written to memory.
If the line is dirty, the data is written back to external memory. If the data has an uncorrectable
error, the words with the error have their WSTRBM AXI signal deasserted. If there is a
correctable error, the line has the error corrected inline before it is written back to memory.
Any uncorrectable errors cause an imprecise abort. An imprecise abort can also be raised on a
correctable error if aborts on RAM errors are enabled in the Auxiliary Control Register.