ARM Cortex R4F - Manual (Page 217)

Level One Memory System
ARM DDI 0363E Copyright © 2009 ARM Limited. All rights reserved. 8-21
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Address decoder faults
The error detection schemes described in this section provide protection against errors that
occur in the data stored in the cache RAMs. Each RAM normally includes a decoder which
enables access to that data and, if an error occurs in this logic, it is not normally detected by these
error detection schemes. The processor includes features that enable it to detect some address
decoder faults. If you are implementing the processor and require these features, contact ARM
to discuss the features and your requirements.
Handling cache parity errors
Table 8-2 shows the behavior of the processor on a cache parity error, depending on bits [5:3]
of the Auxiliary Control Register, see Auxiliary Control Registers on page 4-38.
See Disabling or enabling error checking on page 8-32 for information on how to safely change
these bits.
Hardware recovery
When parity checking is enabled, hardware recovery is always enabled. Memory marked as
write-back write-allocate behaves as write-though. This ensures that cache lines can never be
dirty, therefore the error can always be recovered from by invalidating the cache line that
contains the parity error. The processor automatically performs this invalidation when an error
is detected. The correct data can then be re-read from the L2 memory system.
Parity aborts
If aborts on parity errors are enabled, software is notified of the error by a data abort or prefetch
abort. The error is still automatically corrected by the hardware even if an abort is generated.
If abort generation is not enabled, the hardware recovery is invisible to software. If required,
software can use events and the Correctable Fault Location Register to monitor the errors that
are detected and corrected. See Error detection events on page 8-36 and Correctable Fault
Location Register on page 4-70.
Table 8-2 Cache parity error behavior
Value Behavior
b000 Abort on all parity errors, force write through, enable hardware recovery
b001
b010
b011 Reserved
b100 Disable parity checking
b101 Force write-through, enable hardware recovery, do not generate aborts on parity errors
b110
b111 Reserved